Semiconductor memory devices are generally designed to be resistant to damage from electro-static discharge (ESD) events. The devices may be subjected to ESD testing to verify an appropriate level of ESD immunity. ESD testing of a memory device involves applying transient high voltage stresses to input, output and VDD supply pins of the device relative to a ground potential VSS supply. The device may include an ESD protection circuit having a number of pull-up or pull-down diodes used to limit the amount of applied transient voltage and current which are passed to internal device circuitry. A problem arises when an ESD transient applied to stress an input or output pin passes onto the device VDD supply via the pull-up or pull-down diodes of the ESD protection circuit. This can cause a number of internal circuit parasitics to turn on during an ESD event instead of or in addition to the designated ESD protection circuit. The internal circuit parasitics thus represent "weak spots" which are particularly susceptible to damage during an ESD event.
Exemplary internal circuit parasitics which may turn on before an ESD protection circuit can be formed by: (i) n+ diffusion regions connected to VDD (forming an n+/p-well diode between VDD and VSS); (ii) p+ diffusion regions connected to VSS (forming a p+/n-well diode between VDD and VSS); (iii) an n+ diffusion region connected to VDD adjacent to another n+ diffusion region connected to VSS (forming a parasitic npn bipolar transistor between VDD and VSS); and (iv) a p+ diffusion region connected to VDD adjacent to another p+ diffusion region connected to VSS (forming a parasitic pnp bipolar transistor between VDD and VSS). These and other elements of internal circuit parasitics are susceptible to damage when turned on during an ESD event because layout rules designed to minimize circuit dimensions often result in small contact-to-diffusion-edge and contact-to-gate-edge spacings for VDD contacts. The small spacings are often unable to withstand a large transient current generated during the ESD event. The parasitic turn-on problem is particularly acute in bitline pull-up circuits typically used in static random access memory (SRAM) devices.
FIG. 1 is a schematic diagram of an exemplary prior art bitline pull-up circuit suitable for use in an SRAM device. The pull-up circuit serves to set all bitlines to a common positive voltage to thereby provide faster bitline sensing through a sense amplifier. A number of conventional SRAM bitline pull-up circuits are described in greater detail in U.S. Pat. Nos. 4,639,898 and 5,250,854, which are incorporated by reference herein. The bitline pull-up circuit of FIG. 1 includes a number of N-type MOSFET devices N1 through N4. The source of each of the N-type MOSFETs N1 through N4 is coupled to a corresponding bitline BL1 through BL4. The drains of each of the N-type MOSFETs N1 through N4 are coupled to the VDD supply. The gates of N1 and N2 are coupled to a gate voltage VG1, while the gates of N3 and N4 are coupled to a gate voltage VG2. The two gate voltages may be the same voltage. During a read or write operation involving memory cells coupled to bitlines BL1 through BL4, the gate voltages VG1 and VG2 are raised from a logic "0" level to a logic "1" level to turn on N1 through N4. The bitlines BL1 through BL4 are thereby pulled up via N1 through N4 to a positive voltage which depends on the circuit design. For example, BL1 through BL4 may be pulled up to about 3.5 V in a circuit in which VDD is 5 volts. The N-type devices N1 through N4 in the bitline pull-up circuit of FIG. 1 are generally formed from n+ diffusion regions which, as noted above, can be particularly susceptible to ESD-induced damage.
FIG. 2 shows a conventional layout of the bitline pull-up circuit of FIG. 1. The bitlines BL1 through BL4 are formed from regions 10-1 through 10-4 which may be metallized regions of a first metallization (M1) layer in the memory device. First and second n+ diffusion regions 12, 14 are used to form source and drain regions of the N-type MOSFETs N1 through N4. The diffusion regions 12, 14 represent "active" regions containing separate source regions, drain regions and channels of the MOSFETs N1 through N4. Although these active regions will be generally referred to herein as n+ diffusion regions, it should be understood that a given active region contains not only distinct source and drain diffusion regions for the MOSFETs formed in that region, but also various non-diffusion regions.
The VDD supply is coupled to a VDD region 16 which may also be part of an M1 layer in the memory device. The gate voltage VG1 is coupled to a polysilicon gate region 18 and the gate voltage VG2 is coupled to a polysilicon gate region 20. The gate voltages VG1 and VG2 are coupled to a common voltage source. Contacts 22-1, 22-2, 22-3 and 22-4 connect respective source regions of N-type MOSFETs N1, N2, N3 and N4 formed from the n+ diffusion regions 12 and 14 to the corresponding respective bitline regions 10-1, 10-2, 10-3 and 10-4. VDD contacts 24 connect drain regions of N1 and N4 formed from n+ diffusion region 12 to the VDD region 16, and VDD contacts 26 connect drain regions of N2 and N3 formed from n+ diffusion region 14 to the VDD region 16.
The memory device which includes the pull-up circuit shown in FIG. 2 generally includes a p-well connected to the VSS supply of the device. The n+ diffusion regions 12, 14 form n+/p-well diodes with this p-well connected to VSS. As noted above, the n+/p-well diodes represent a weak link between VDD and VSS, and are susceptible to damage during an ESD event when the n+ diffusion regions 12, 14 and contacts 22-1, 22-2, 22-3, 22-4, 24 and 26 are arranged in a conventional layout such as that shown in FIG. 2. The conventional layout generally places the VDD contacts 24 and 26 in VDD region 16 relatively close to the edge of the respective n+ diffusion regions 12, 14 in order to optimize the chip layout. During an ESD event, if the n+/p-well diode breaks down due to the transient high voltage between VDD and VSS, then the ESD current flowing through the n+/p-well diode will raise the local temperature of the diode junction around the edge of the n+ diffusion region 12, 14. When the VDD contacts 24 and 26 are too close to the n+ diffusion edge, the metal at these contacts can easily reach a melting temperature (e.g., 550.degree. C. for the eutectic temp of Al-Si interdiffusion), thus causing metal spiking and contact leakage. Similar problems result from restrictions on maximum contact-to-gate-edge spacing for the VDD contacts in the conventional bitline pull-up circuit layout of FIG. 2. The use of the FIG. 2 layout in a memory device therefore renders the device particularly susceptible to ESD-induced internal circuit damage.
As is apparent from the above, a need exists for an improved bitline pull-up circuit layout in which the contact-to-diffusion-edge and contact-to-gate-edge spacings can be increased for VDD contacts such that the device exhibits enhanced immunity to ESD damage, without violating device dimension and chip area restrictions.